/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2021-2022, Pensando Systems Inc.
 */

#ifndef __ASIC_REGS_ELBA_H__
#define __ASIC_REGS_ELBA_H__

#ifdef __cplusplus
extern "C" {
#if 0
} /* close to calm emacs autoindent */
#endif
#endif

#define ASIC_(REG)      ELB_ ##REG
#define PXB_(REG) \
    (ELB_ADDR_BASE_PXB_PXB_OFFSET + ELB_PXB_CSR_ ##REG## _BYTE_ADDRESS)
#define _PXC_BASE(pn) \
    (ELB_ADDR_BASE_PP_PXC_0_OFFSET + \
     ((pn) * ELB_ADDR_BASE_PP_PXC_0_SIZE))
#define PXC_(REG, pn) \
    (_PXC_BASE(pn) + ELB_PXC_CSR_ ##REG## _BYTE_ADDRESS)

/* elb_top_csr_defines.h */
#define ELB_ADDR_BASE_PXB_PXB_OFFSET 0x20000000
#define ELB_ADDR_BASE_PP_PXC_0_OFFSET 0x20100000
#define ELB_ADDR_BASE_PP_PXC_0_SIZE 0x40000
#define ELB_ADDR_BASE_INTR_INTR_OFFSET 0x61800000

/* elb_pxb_c_hdr.h */
#define ELB_PXB_CSR_DHS_TGT_NOTIFY_BYTE_ADDRESS 0xc4000
#define ELB_PXB_CSR_DHS_ITR_PCIHDRT_BYTE_ADDRESS 0x8000
#define ELB_PXB_CSR_DHS_TGT_PMT_BYTE_ADDRESS 0x18000
#define ELB_PXB_CSR_DHS_TGT_PMR_BYTE_ADDRESS 0x20000
#define ELB_PXB_CSR_DHS_TGT_PRT_BYTE_ADDRESS 0x30000
#define ELB_PXB_CSR_DHS_TGT_AXIMST0_BYTE_ADDRESS 0x62000
#define ELB_PXB_CSR_DHS_TGT_AXIMST1_BYTE_ADDRESS 0x63000
#define ELB_PXB_CSR_DHS_TGT_IND_RSP_ENTRY_BYTE_ADDRESS 0xc4020
#define ELB_PXB_CSR_CFG_TGT_REQ_NOTIFY_INT_BYTE_ADDRESS 0xc4160
#define ELB_PXB_CSR_CFG_TGT_REQ_NOTIFY_RING_SIZE_BYTE_ADDRESS 0xc4170
#define ELB_PXB_CSR_CFG_TGT_REQ_INDIRECT_INT_BYTE_ADDRESS 0xc4180
#define ELB_PXB_CSR_CFG_TGT_NOTIFY_EN_BYTE_ADDRESS 0xc41c4
#define ELB_PXB_CSR_CFG_TGT_PMT_GRST_BYTE_ADDRESS 0xc4244
#define ELB_PXB_CSR_STA_TGT_IND_INFO_BYTE_ADDRESS 0xc43c0
#define ELB_PXB_CSR_DHS_ITR_PCIHDRT_ENTRIES 0x800
#define ELB_PXB_CSR_DHS_ITR_PCIHDRT_ENTRY_BYTE_SIZE 0x10
#define ELB_PXB_CSR_DHS_TGT_PMT_ENTRY_ARRAY_ELEMENT_SIZE 0x1
#define ELB_PXB_CSR_DHS_TGT_PMR_ENTRY_BYTE_SIZE 0x10
#define ELB_PXB_CSR_DHS_TGT_PRT_ENTRY_BYTE_SIZE 0x10

/* elb_pxc_c_hdr.h */
#define ELB_PXC_CSR_DHS_C_MAC_APB_ENTRY_BYTE_ADDRESS 0x1000

/* elb_intr_c_hdr.h */
#define ELB_INTR_CSR_DHS_INTR_ASSERT_ENTRY_ARRAY_COUNT 0x2000
#define ELB_INTR_CSR_DHS_INTR_MSIXCFG_BYTE_OFFSET 0x20000
#define ELB_INTR_CSR_DHS_INTR_FWCFG_BYTE_OFFSET 0x40000
#define ELB_INTR_CSR_DHS_INTR_DRVCFG_BYTE_OFFSET 0x80000
#define ELB_INTR_CSR_DHS_INTR_ASSERT_BYTE_OFFSET 0xd0000
#define ELB_INTR_CSR_DHS_INTR_STATE_BYTE_OFFSET 0xe0000

#ifdef __cplusplus
}
#endif

#endif /* __ASIC_REGS_ELBA_H__ */
